An integrated circuit, referred to as a very large scale integrated (VLSI) circuit, includes a large number of circuit elements as part of a single device. A VLSI device, referred to as an application specific integrated circuit (ASIC), is configured to operate in a single application. An ASIC can be built as a circuit with multiple, independent functions and as a system-on-a-chip, which contains a core processor, memory, and peripheral logic elements all on the same substrate. Testing a VLSI device can be difficult due to the complexity of the device and limited access to internal nodes provided by external device pins.
In one test configuration, a device is tested functionally. Functional testing is accomplished by driving device inputs with test vectors and checking device outputs for responses. In the case of combinational logic, a set of test vectors can be defined to exercise all possible logic states. In the case of a device having storage elements, the task can be significantly more complex. For a device having storage elements, test vectors can be developed to clock the storage elements to known states. However, deriving a substantially exhaustive set of functional test vectors can become a design exercise rivaling the design of the device itself. In this case, developing functional test vectors can represent a significant development cost.
To simplify the task of deriving test vectors, design for test (DFT) philosophies have developed to make a device more testable without recourse to functional test vectors. In one such philosophy, referred to as scan testing, all storage elements within a device operate in a normal mode and a test mode. In the normal mode, the device operates to perform application functions. In the test mode, the storage elements are configured into scan chains capable of receiving control signals to act like a shift register. The device can then be regarded as relatively simple combinational logic between shift register stages. The combinational logic provides inputs to the storage elements, and the storage elements provide inputs to the combinational logic. A test input is provided at one end of each scan chain to load the shift register, and a test output is provided at the other end of each scan chain to unload the shift register. After loading the scan chains in the test mode, the device is switched to the normal mode and clocked. Next, the scan chains are unloaded in the test mode to check responses. The combinational logic and storage elements can be tested without regard to the overall functionality of the device.
Scan testing simplifies the task of deriving test vectors for the device. However, scan chains through a large device can become excessively long, resulting in clock skew problems from one edge of the device to the other. Also, the number of test vectors for ample fault coverage can become excessive. Long scan chains and large test vector sets result in long test times, which increase the cost of the device. The device costs can be prohibitive for low production quantities and the ASIC market.